comp.lang.vhdl - VHSIC Hardware Description Language, IEEE 1076/87.
Hi, How to print std_logic_vector variable into hex string in VHDL? Thanks, Carson
What is the best way to write a series of delayed std_logic_vectors to replace the verbose code below: if(clk'event and clk='1')then data_1 <= data_in; data_2 <= data_1; data_3 <= data_2; etc. Thanks, Brad Smallridge aivision
I have been working on CIDFonts for quite some time. Earlier I was able to create and embed CIDFonts in Postscript files in Binary format. Now I have a problem that I want to output these as Hex(ASCII) as my required data format is Clean7Bit. Though Adobe's document says we can write CID font data as Hex like this %%BeginData: 6291044 Hex Bytes (Hex) 3097117 StartData But it doesn't work here when I try to do so. On contacting Adobe I was discouraged to use this hex format also there is no sample available for this. So I want to know is there some way to do so by changing the font architecture or like that. Regards, Muhammad Nadeem Maqsood
I've been searching here but all the hits were for converting SLV to string for testbenches. I'm looking to convert a string to an array of 8bit SLVs. The idea is I have a revision string of fixed length- something like: ver <= "005-0805300908x2"' and I have an array of registers declared as such: SUBTYPE hwid_type is STD_LOGIC_VECTOR(7 DOWNTO 0); TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type; SIGNAL regs : reg_type; What I'm looking for is a loop shown here in psuedo code: for i in 1 to 16 loop regs(i) <= to_slv(ver(mid$(i,1))) end loop Note this is for synthesis so I don't know if any of this is even legal. I am trying to create a version register that the microprocessor can read. An ascii string is prefered - let's pretend for a moment it is a requirement. This is also a learning exercise for me to deal with strings in VHDL. Any ideas? Shannon