comp.lang.vhdl - VHSIC Hardware Description Language, IEEE 1076/87.
Just a short question to the VHDL experts. Assume we have the following TestBench ------- library IEEE; use IEEE.std_logic_1164.all; entity TestBench is end TestBench; architecture behaviour of TestBench is signal test : STD_LOGIC := '0'; begin test <= transport '1' after 3 ns; test <= transport '0' after 5 ns; end behaviour; ------ Now which output wave-form is expected for "test" ? I thought it should be: 0 at 0 ns (initial value because of declaration) 1 at 3 ns (first signal assignment becomes active). X at 5 ns (two drivers '1' and '0', resolved to 'X'). But running it through a VHDL simulator gave 0 at 0 ns X at 3 ns X at 5 ns Now I'm not at all sure why that happens and what the correct waveform is for the "test" signal according to the VHDL2000 language reference. Is this a bug in the VHDL simulator or what ? Any comments ? so long lundril
Hi there, is anybody aware of a way to model a wired-or signal resolution function which can be synthesized with XST? As far as I know XST does not support user-defined resolution functions, however I need a wired-or functionality in my design. Regards Dominik
Hey everyone, I'm kinda a newbie in VHDL programming. And I don't know what this error means in my case, here is what I have : type tab_aud_samp is array (NATURAL range <>) of std_logic_vector(31 downto 0); function clear_table(h : tab_aud_samp) return std_logic_vector is variable aux : std_logic_vector (31 downto 0); begin aux := X"00000000"; for i in 0 to h'length-1 loop h(i) <= aux; end loop; return aux; end clear_table; I didn't know how to clear this table in only one clock some other way. And it tells me that when I do h(i) <= aux; "Target of signal assignment is not a signal" Do you know what it means ? What I should do ? Thanks a lot. Nicolas