vhdl >> shift/rotate operator for std_logic_vector

by Marteno Rodia » Wed, 13 Jun 2007 04:49:51 GMT

I mean operators like ror, rol, sla, sra, srl, sll.
Are they overloaded for std_logic_vector type in any 'standard' package?

I use Altera Quartus 6.1, and I recieive a message:
"Error (10327): VHDL error at vector_selector.vhd(191): can't determine
definition of operator ""srl"" -- found 0 possible definitions".

MR

vhdl >> shift/rotate operator for std_logic_vector

by Mike Treseler » Wed, 13 Jun 2007 05:24:26 GMT



Let's have a look at the source:
http://www.eda.org/rassp/vhdl/models/standards/numeric_std.vhd

The shifts work differently for
signed vs unsigned. Thats also why sla and sra are
not defined. The vector type covers it.

But it's not hard to cast out the
numeric interpretation when the math is done:

my_slv <= std_logic_vector(my_uns_vec srl 1);


That the right answer. There is no srl defined for std_logic_vector.

-- Mike Treseler

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