### verilog >> 32-bit adder (CLA)

Hello,

I'm currently assinged a school project to implenent a 32-bit Adder

The reasone I've posted on this group is because I need to know if
there is any suggestion which could be helpful. It must be implemented
in Verilog. However, first I need the theory then I may go for
simulation and documentation.

Please let me know if there is a good help on net.

Thanks,
Amit

### verilog >> 32-bit adder (CLA)

Doesn't matter what you want to design the first step is learn the
theory as otherwise it will be somewhat difficult to implement
something you have no clue what and how.

Adder usually are done in two way, one which consume minimum amount of
logic however each bit need to wait for the prior step in order to
calculate its value and therefore the longer the adder the more delay
for the last bit.
In order to achieve for same adder higher frequency of operation a
parallel calculation implementation is the second solution and as can
be expected the drawback is more logic.

One technique you might want to use when trying to "figure" new
issue is not work with big design/number but rather with small block.

So take for example 1 bit adder.
A which is one bit
B which is one bit
Than let say
S is the sum
And
C is the carry
{C,S}=A+B
if you look on the actual logic and check all 4 combination of A and B
it will come to be
S = A ^ B (Where ^ is XOR)
C = A & B

A+B = C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Now lets make A and B 2 bit

A + B = C S
00 00 0 00
00 01 0 01
00 10 0 10
00 11 0 11
01 00 0 01
01 01 0 10
01 10 0 11
01 11 1 00
10 00 0 10
10 01 0 11
10 10 1 00
10 11 1 01
11 00 0 11
11 01 1 00
11 10 1 01
11 11 1 10

therefore
C = 1 when A,B are 01,11 or 10,10 or 10,11 or 11,01 or 11,10 or 11,11
Similary you can do for S bit 0 and S bit 1

Than using Carno map you can minimize the above and find the equation

On the other hand if you want to use minimum logic and the speed is not
an issue than the solution is by building the 2 bit using 1 bit block.

However while the first bit is made of half adder meaning only A and B
as input all the next bit are made of full adder which mean the
appropriate bit for A and B as well as pervious stage carry

Therefore
{C[0],S[0]} = A[0] + B[0]
which we already saw it is like
S[0] = A[0] ^ B[0]
C[0] = A[0] & B[0]

However for second bit
{C[1],S[1]}=A[1]+B[1]+C[0]
Which is actual will be
A[1],B[1],C[0] C[1],S[1]
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
And I will leave it to you to find the exact equation

Now back to your 32 bit if you use the minimum logic approach than the
first bit is like the 2 bit example and any of the other 31 bit are
like the second bit of the 2 bit example.

{C[0],S[0]} = A[0] + B[0]
{C[1],S[1]}=A[1]+B[1]+C[0]
...
{C[31],S[31]}=A[31]+B[31]+C[30]

However if you look for the maximum speed implementation than you need
to do much more work as than you need to find like we did for the 2 bit
what is the equation for each bit of the result base on the whole bit
of A and B.

I believe though I might be mistaken that most synthesis tool will
synthesis A+B to be the fast adder however by adding constrain you can
usually force them to generate minimum logic implementation.

Have fun.

```For some reason I am having problems with the output of this code for
the Carry-look-ahead and half adder. It took me some time to code it
and now I am having issues getting the correct wave outputs. Please
help me!! My test bench is include.
================================================================
//Verilog Code: 4-bit CLA adder (CLA.v)

input  a, b;
output c_out, sum;

assign {cout,sum}= a + b;

endmodule

module cla4(c_output,c_in_0,g,p);

input        c_in_0;
output [3:0] c_output;   //declare 4-bit carry output
reg    [3:0] c_output;     //declare 4-bit carry output as reg for
always process
input  [3:0] g;        //declare 4-bit input (g)
input  [3:0] p;        //declare 4-bit input (p)

always @ (g or p)       //start process, which starts soon as input
changes
begin
c_output[1] = g[0] + p[0]*c_in_0;       //first equation,
c_output[2] = g[1] + p[1]* (g[0] + p[0]*c_in_0);  //second
equation,
c_output[3] = g[2] + p[2]* (g[1] + p[1]* (g[0] +
p[0]*c_in_0) );  //third equation
end

endmodule

module TOP_MOD(a,b,s,in_bit);

input  [3:0] a;
input  [3:0] b;
input        in_bit;
output [3:0] s; //final output values

wire   [3:0] p;
wire   [3:0] g;
wire   [2:0] out_cla; //for the inputs of xor gates

cla4 U4(.c_output(out_cla), .c_in_0(in_bit), .g(g), .p(p));

assign s[0]= p[0]^in_bit;
assign s[1]= p[1]^out_cla[1];
assign s[2]= p[2]^out_cla[2];
assign s[3]= p[3]^out_cla[3];

endmodule
===============================================================
//Verilog Code: Testbench for CLA (CLA_tb.v)

module TB_CLA( );

parameter In_width_a  = 4;
parameter In_width_b  = 4;
parameter Out_width_s = 4;

reg[In_width_a-1:0]in_a_tb;
reg[In_width_b-1:0]in_b_tb;
reg c_in;
wire[Out_width_s-1:0]out_s_tb;

TOP_MOD U0(.a(in_a_tb),.b(in_b_tb),.s(out_s_tb),.in_bit(c_in));

initial
begin
in_a_tb = 4'b0000;
in_b_tb = 4'b0000;
c_in = 1'b0;
#50   in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50   in_a_tb = 4'b0011; in_b_tb = 4'b0010; c_in = 1'b1;
#50   in_a_tb = 4'b0001; in_b_tb = 4'b0000; c_in = 1'b0;
#50   in_a_tb = 4'b0111; in_b_tb = 4'b0000; c_in = 1'b1;
#50   in_a_tb = 4'b1111; in_b_tb = 4'b0001; c_in = 1'b0;
#50   in_a_tb = 4'b0101; in_b_tb = 4'b0010; c_in = 1'b1;
#50   \$stop;
#20   \$finish;
end

endmodule
================================================================

```

``` Can a 16-bit Clarion application call a 32-bit Clarion dll?

We have a rather big 16-bit app that will take some time to convert to
32-bit, but would like to start calling 32-but dll's (that we develop
ourselves) from this app.

```

```Hi,

I'm trying to use uint64_t by #including stdint.h in C on 32-bit
machine. However,  I can't seem to get the right value for shifting,
for example:

for(i = 0; i < 64; i++)
{
c = 1 << i;
printf(" %d : %x\n", i, c);
}

gives the following output

0 : 1
1 : 2
2 : 4
3 : 8
4 : 10
5 : 20
6 : 40
7 : 80
8 : 100
9 : 200
10 : 400
11 : 800
12 : 1000
13 : 2000
14 : 4000
15 : 8000
16 : 10000
17 : 20000
18 : 40000
19 : 80000
20 : 100000
21 : 200000
22 : 400000
23 : 800000
24 : 1000000
25 : 2000000
26 : 4000000
27 : 8000000
28 : 10000000
29 : 20000000
30 : 40000000
31 : 80000000
32 : 1
33 : 2
34 : 4
35 : 8
36 : 10
37 : 20
38 : 40
39 : 80
40 : 100
41 : 200
42 : 400
43 : 800
44 : 1000
45 : 2000
46 : 4000
47 : 8000
48 : 10000
49 : 20000
50 : 40000
51 : 80000
52 : 100000
53 : 200000
54 : 400000
55 : 800000
56 : 1000000
57 : 2000000
58 : 4000000
59 : 8000000
60 : 10000000
61 : 20000000
62 : 40000000
63 : 80000000

Anyone know what the problem is, and what the correct solution is for
such use?

Thanks,
-Seung

```