Hello,

I'm currently assinged a school project to implenent a 32-bit Adder

(CLA or Carry Look Ahead).

The reasone I've posted on this group is because I need to know if

there is any suggestion which could be helpful. It must be implemented

in Verilog. However, first I need the theory then I may go for

simulation and documentation.

Please let me know if there is a good help on net.

Thanks,

Amit

Doesn't matter what you want to design the first step is learn the

theory as otherwise it will be somewhat difficult to implement

something you have no clue what and how.

Adder usually are done in two way, one which consume minimum amount of

logic however each bit need to wait for the prior step in order to

calculate its value and therefore the longer the adder the more delay

for the last bit.

In order to achieve for same adder higher frequency of operation a

parallel calculation implementation is the second solution and as can

be expected the drawback is more logic.

One technique you might want to use when trying to "figure" new

issue is not work with big design/number but rather with small block.

So take for example 1 bit adder.

A which is one bit

B which is one bit

Than let say

S is the sum

And

C is the carry

And the adder is

{C,S}=A+B

if you look on the actual logic and check all 4 combination of A and B

it will come to be

S = A ^ B (Where ^ is XOR)

C = A & B

A+B = C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Now lets make A and B 2 bit

A + B = C S

00 00 0 00

00 01 0 01

00 10 0 10

00 11 0 11

01 00 0 01

01 01 0 10

01 10 0 11

01 11 1 00

10 00 0 10

10 01 0 11

10 10 1 00

10 11 1 01

11 00 0 11

11 01 1 00

11 10 1 01

11 11 1 10

therefore

C = 1 when A,B are 01,11 or 10,10 or 10,11 or 11,01 or 11,10 or 11,11

Similary you can do for S bit 0 and S bit 1

Than using Carno map you can minimize the above and find the equation

for the parallel adding.

On the other hand if you want to use minimum logic and the speed is not

an issue than the solution is by building the 2 bit using 1 bit block.

However while the first bit is made of half adder meaning only A and B

as input all the next bit are made of full adder which mean the

appropriate bit for A and B as well as pervious stage carry

Therefore

{C[0],S[0]} = A[0] + B[0]

which we already saw it is like

S[0] = A[0] ^ B[0]

C[0] = A[0] & B[0]

However for second bit

{C[1],S[1]}=A[1]+B[1]+C[0]

Which is actual will be

A[1],B[1],C[0] C[1],S[1]

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

And I will leave it to you to find the exact equation

Now back to your 32 bit if you use the minimum logic approach than the

first bit is like the 2 bit example and any of the other 31 bit are

like the second bit of the 2 bit example.

{C[0],S[0]} = A[0] + B[0]

{C[1],S[1]}=A[1]+B[1]+C[0]

...

{C[31],S[31]}=A[31]+B[31]+C[30]

However if you look for the maximum speed implementation than you need

to do much more work as than you need to find like we did for the 2 bit

what is the equation for each bit of the result base on the whole bit

of A and B.

I believe though I might be mistaken that most synthesis tool will

synthesis A+B to be the fast adder however by adding constrain you can

usually force them to generate minimum logic implementation.

Have fun.

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